Google Scholar.

Selected Recent Works

• HOST’26 PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference

• RAID’25 ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors

• ICML’25 Taming Diffusion for Dataset Distillation with High Representativeness

• ICML’25 Graph Generative Pre-trained Transformer

• DAC’25 Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture

• DAC’25 Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning

• NDSS’25 Probe-Me-Not: Protecting Pre-trained Encoders from Malicious Probing

• NeurIPS’24 GraphCroc: Cross-Correlation Autoencoder for Graph Structural Reconstruction

• NeurIPS’24 Bileve: SecuringText Provenancein Large Language Models Against Spoofing with Bi-level Signature

• ICCAD’24 AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge Computing

• ICLR’24 ArchLock: Locking DNN Transferability at the Architecture Level with a Zero-Cost Binary Predictor

• ASPLOS’24 An Ultra-Lightweight Vector Symbolic Architecture-based Classifier Library for Tiny Microcontrollers

• Oakland’24 Side-Channel-Assisted Reverse-Engineering of Encrypted DNN Hardware Accelerator IP and Attack Surface Exploration

• Oakland’24 DeepShuffle: A Lightweight Defense Framework against Adversarial Fault Injection Attacks on Deep Neural Networks in Multi-Tenant Cloud-FPGA

• DAC’24 TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments

• tinyML’24 Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfaces

• NeurIPS’23 Structural Linearized Graph Convolutional Network for Homomorphically Encrypted Inference

• MICRO’23 AQ2PNN: Two-party Privacy-Preserving Deep Neural Network Inference with Adaptive Quantization

• ICCV’23 VertexSerum: Poisoning Graph Neural Networks for Link Inference

• ICCV’23 AutoReP: Automatic ReLU Replacement for Fast Private Network Inference

• ICCAD’23 MirrorNet: A TEE-Friendly Framework for Secure On-device DNN Inference

• ICML’23 NNSplitter: An Active Defense Solution to DNN Model via Automated Weight Obfuscation

• ICML’23 Orchestrating Encoding and Sparsity for Fast Homomorphically Encrypted NN Inference

• DAC’23 A Lightweight Defense Framework against RowHammer Attack on Deep Neural Networks

• DAC’23 Polynomial Arch. Search Framework for Two-party Computation-based Secure NN Deployment

• tinyML’23 MetaLDC: Meta Learning of Low-Dimensional Computing Classifiers for Fast On-Device Adaption

• ICCAD’22 ObfuNAS: A Neural Architecture Search-based DNN Obfuscation Approach [IEEE/ACM William J. McCalla ICCAD Best Paper Nomination]

• DAC’22 LeHDC: Learning-Based Hyperdimensional Computing Classifier

• DAC’22 Exploiting Privileged Encoding to Protect Hyperdimensional Computing Models against IP Stealing

• ESWEEK’22 Response Feedback-based Lightweight Anti-Machine Learning-Attack PUF [Best Paper Nomination]

• tinyML’22 A Brain-Inspired Low-Dimensional Computing Classifier for Inference on Tiny Devices [Video]

• FCCM’22 A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering

• Security’21 An Adversarial Weight Duplication Attack Framework to Crush DNN in Multi-Tenant FPGA

• TODAES’21 FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA [TODAES Rookie Author of the Year (RAY) Award]

• DAC’21 DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA

• DAC’21 SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture

• CHES’20 CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme [Video]

2026

• PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference
  Nuntipat Narkthong, Xiaolin Xu
  IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2026
  

2025

• ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
  Nuntipat Narkthong, Yukui Luo, Xiaolin Xu
  International Symposium on Research in Attacks, Intrusions and Defenses (RAID), 2025
  

• Graph Generative Pre-trained Transformer
  Xiaohui Chen, Yinkai Wang, Jiaxing He, Yuanqi Du, Soha Hassoun, Xiaolin Xu, Liping Liu
  International Conference on Machine Learning (ICML) 2025
  

• Taming Diffusion for Dataset Distillation with High Representativeness
  Lin Zhao, Yushu Wu, Xinru Jiang, Jianyang Gu, Yanzhi Wang, Xiaolin Xu, Pu Zhao, Xue Lin
  International Conference on Machine Learning (ICML) 2025
  

• Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
  Shijin Duan, Nuntipat Narkthong, Yukui Luo, Shaolei Ren and Xiaolin Xu
  IEEE/ACM Design Automation Cnference (DAC) 2025. (Acceptance Rate: 23%)
  

• Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
  Shijin Duan, Gaowen Liu, Charles Fleming, Ramana Rao Kompella, Xiaolin Xu and Shaolei Ren
  IEEE/ACM Design Automation Cnference (DAC) 2025. (Acceptance Rate: 23%)
  

• Graph Generative Pre-trained Transformer
  Xiaohui Chen, Yinkai Wang, Jiaxing He, Yuanqi Du, Soha Hassoun, Xiaolin Xu, Liping Liu
  ICLR Workshop on Deep Generative Model in Machine Learning: Theory, Principle and Efficacy (DeLTa), 2025.
  

• Large Language Model is Secretly a Protein Sequence Optimizer
  Yinkai Wang, Jiaxing He, Yuanqi Du, Xiaohui Chen, Jianan Canal Li, Li-Ping Liu, Xiaolin Xu, Soha Hassoun
  ICLR Workshop on Learning Meaningful Representations of Life (LMRL), 2025.

• ProDiF: Protecting Domain-Invariant Features to Secure Pre-Trained Models Against Extraction
  Tong Zhou, Shijin Duan, Gaowen Liu, Charles Fleming, Ramana Rao Kompella, Shaolei Ren, Xiaolin Xu
  ICLR Workshop on Weight Space Learning, 2025

• Towards Vector Optimization on Low-Dimensional Vector Symbolic Architecture
  Shijin Duan, Yejia Liu, Gaowen Liu, Ramana Rao Kompella, Shaolei Ren, Xiaolin Xu
  Conference on Parsimony and Learning (CPAL), 2025

• Probe-Me-Not: Protecting Pre-trained Encoders from Malicious Probing
  Ruyi Ding, Tong Zhou, Lili Su, Adam Ding, Xiaolin Xu, Yunsi Fei
  Network and Distributed System Security Symposium (NDSS), 2025. (Acceptance Rate: 16.1%)

2024

• Bileve: SecuringText Provenancein Large Language Models Against Spoofing with Bi-level Signature
  Tong Zhou, Xuandong Zhao, Xiaolin Xu, Shaolei Ren
  Conference on Neural Information Processing Systems (NeurIPS), 2024 (Acceptance Rate: 25.8%)

• GraphCroc: Cross-Correlation Autoencoder for Graph Structural Reconstruction
  Shijin Duan, Ruyi Ding, Jiaxing He, Aidong Adam Ding, Yunsi Fei, Xiaolin Xu
  Conference on Neural Information Processing Systems (NeurIPS), 2024 (Acceptance Rate: 25.8%)

• AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge Computing
  Tong Zhou, Jiahui Zhao, Yukui Luo, Xi Xie, Wujie Wen, Caiwen Ding, Xiaolin Xu
  IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2024 (Acceptance Rate: 24%)
  

• Watch Out for the Inherent Vulnerabilities in Developing Multi-tenant Cloud-FPGA: Communication Protocols
  Ziyu Liu, Yukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu
  ACM Transactions on Design Automation of Electronic Systems (TODAES), 2024
  

• ALLI/O: An Action-based Visual Programming Language for Embedded System Programming
  Nuntipat Narkthong, Chattriya Jariyavajee, Xiaolin Xu
  IEEE Symposium on Visual Languages and Human-Centric Computing (VL/HCC), 2024
  

• MicroVSA: An Ultra-Lightweight Vector Symbolic Architecture-based Classifier Library for Tiny Microcontrollers
  Nuntipat Narkthong, Shijin Duan, Shaolei Ren, Xiaolin Xu
  ACM Conference on Architectural Support for Programming Languages and Operating Systems, (ASPLOS) 2024 (Acceptance Rate: 18.4%)
  Three artifact badges (available, functional, reproduced) received

• DeepShuffle: A Lightweight Defense Framework against Adversarial Fault Injection Attacks on Deep Neural Networks in Multi-Tenant Cloud-FPGA
  Yukui Luo, Adnan Siraj Rakin, Deliang Fan, Xiaolin Xu
  IEEE Symposium on Security and Privacy (S&P), Oakland 2024 (Acceptance Rate: 17.8%)

• Side-Channel-Assisted Reverse-Engineering of Encrypted DNN Hardware Accelerator IP and Attack Surface Exploration
  Gongye Cheng, Yukui Luo, Xiaolin Xu, Yunsi Fei
  IEEE Symposium on Security and Privacy (S&P), Oakland 2024 (Acceptance Rate: 17.8%)

• TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments
  Ziyu Liu, Tong Zhou, Yukui Luo, Xiaolin Xu
  IEEE/ACM Design Automation Cnference (DAC) 2024. (Acceptance Rate: 23%)
  

• ArchLock: Locking DNN Transferability at the Architecture Level with a Zero-Cost Binary Predictor
  Tong Zhou, Shaolei Ren, Xiaolin Xu
  International Conference on Learning Representations (ICLR), 2024 (Acceptance Rate: 30.9%)

• Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfaces
  Yejia Liu, Shijin Duan, Xiaolin Xu, Shaolei Ren
  tinyML Research Symposium (tinyML) 2024.
  

• Neural Architecture Search for Adversarial Robustness via Learnable Pruning
  Yize Li, Pu Zhao, Ruyi Ding, Tong Zhou, Yunsi Fei, Xiaolin Xu, Xue Lin
  Frontiers in High Performance Computing, 2024.

2023

• LinGCN: Structural Linearized Graph Convolutional Network for Homomorphically Encrypted Inference
  Hongwu Peng, Ran Ran, Yukui Luo, Jiahui Zhao, Shaoyi Huang, Kiran Thorat, Tong Geng, Chenghong Wang, Xiaolin Xu, Wujie Wen, Caiwen Ding
  Thirty-seventh Conference on Neural Information Processing Systems (NeurIPS), 2023 (Acceptance Rate: 26.1%)

• AQ2PNN: Enabling Two-party Privacy-Preserving Deep Neural Network Inference with Adaptive Quantization
  Yukui Luo, Nuo Xu, Hongwu Peng, Chenghong Wang, Shijin Duan, Kaleel Mahmood, Wujie Wen, Caiwen Ding, Xiaolin Xu
  IEEE/ACM International Symposium on Microarchitecture (MICRO), 2023 (Acceptance Rate: 23.8%)

• VertexSerum: Poisoning Graph Neural Networks for Link Inference
  Ruyi Ding*, Shijin Duan*, Xiaolin Xu, Yunsi Fei
  International Conference on Computer Vision (ICCV) 2023 (Acceptance Rate: 26.15%)

• AutoReP: Automatic ReLU Replacement for Fast Private Network Inference
  Hongwu Peng*, Shaoyi Huang*, Tong Zhou*, Yukui Luo, Chenghong Wang, Zigeng Wang, Jiahui Zhao, Xi Xie, Ang Li, Tony Geng, Kaleel Mahmood, Wujie Wen, Xiaolin Xu, Caiwen Ding
  International Conference on Computer Vision (ICCV) 2023 (Acceptance Rate: 26.15%)

• MirrorNet: A TEE-Friendly Framework for Secure On-device DNN Inference
  Ziyu Liu, Yukui Luo, Shijin Duan, Tong Zhou and Xiaolin Xu
  IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2023 (Acceptance Rate: 22.9%)

• NNSplitter: An Active Defense Solution to DNN Model via Automated Weight Obfuscation
  Tong Zhou, Yukui Luo, Shaolei Ren, Xiaolin Xu
  International Conference on Machine Learning (ICML), 2023 (Acceptance Rate: 27.9%)

• MetaLDC: Meta Learning of Low-Dimensional Computing Classifiers for Fast On-Device Adaption
  Yejia Liu, Shijin Duan, Xiaolin Xu, Shaolei Ren
  tinyML Research Symposium 2023

• SpENCNN: Orchestrating Encoding and Sparsity for Fast Homomorphically Encrypted Neural Network Inference
  Ran Ran, Xinwei Luo, Wei Wang, Tao Liu, Gang Quan, Xiaolin Xu, Caiwen Ding, Wujie Wen
  International Conference on Machine Learning (ICML), 2023 (Acceptance Rate: 27.9%)

• Achieving Certified Robustness for Brain-Inspired Low-Dimensional Computing Classifiers
  Fangfang Yang, Shijin Duan, Xiaolin Xu, and Shaolei Ren
  International Workshop on AI-Driven Trustworthy, Secure, and Privacy-Preserving Computing (AidTSP) 2023.
  

• HammerDodger: A Lightweight Defense Framework against RowHammer Attack on Deep Neural Networks
  Cheng Gongye, Yukui Luo, Xiaolin Xu, and Yunsi Fei
  IEEE/ACM Design Automation Cnference (DAC) 2023. (Acceptance Rate: 23%)
  

• PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment
  Hongwu Peng, Shanglin Zhou, Yukui Luo, Nuo Xu, Shijin Duan, Ran Ran, Jiahui Zhao, Chenghong Wang, Tong Geng, Wujie Wen, Xiaolin Xu, and Caiwen Ding
  IEEE/ACM Design Automation Cnference (DAC) 2023. (Acceptance Rate: 23%)
  

2022

• A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure
  Yukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu
  International Conference on Field Programmable Technology (FPT), 2022.

• A Neural Architecture Search-based DNN Obfuscation Approach
  Tong Zhou, Shaolei Ren, Xiaolin Xu
  IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022 (Acceptance Rate: 22%)
  IEEE/ACM William J. McCalla ICCAD Best Paper Nomination

• FLAM-PUF: A Response Feedback-based Lightweight Anti-Machine Learning-Attack PUF
  Linjun Wu, Yupeng Hu, Kehuan Zhang, Wenjia Li, Xiaolin Xu, Wanli Chang
  International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), part of the Embedded Systems Week (ESWEEK), 2022 (Acceptance Rate: 22%)
  Best Paper Award Nomination
  

• NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering
  Yukui Luo, Shijin Duan, Cheng Gongye, Yunsi Fei, Xiaolin Xu
  IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2022 (Acceptance Rate: 20%)

• LeHDC: Learning-Based Hyperdimensional Computing Classifier [Code]
  Shijin Duan, Yejia Liu, Shaolei Ren, Xiaolin Xu
  IEEE/ACM Design Automation Cnference (DAC) 2022. (Acceptance Rate: 23%)
  

• HDLock: Exploiting Privileged Encoding to Protect Hyperdimensional Computing Models against IP Stealing
  Shijin Duan, Shaolei Ren, Xiaolin Xu
  IEEE/ACM Design Automation Cnference (DAC) 2022. (Acceptance Rate: 23%)
  

• A Brain-Inspired Low-Dimensional Computing Classifier for Inference on Tiny Devices
  Shijin Duan, Xiaolin Xu, Shaolei Ren
  tinyML Research Symposium 2022
  

• An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA
  Yukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu
  ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2022, (poster)
  

2021

• Deep Neural Network Security from A Hardware Perspective
  Tong Zhou, Yuheng Zhang, Shijin Duan, Yukui Luo, Xiaolin Xu,
  IEEE/ACM Symposium on Nanoscale Architectures, NANOARCH 2021
  

• HDCOG: A Lightweight Hyperdimensional Computing Framework with Feature Extraction
  Shijin Duan, Xiaolin Xu
  IEEE/ACM Symposium on Nanoscale Architectures, NANOARCH 2021
  

• Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA
  Adnan Siraj Rakin*, Yukui Luo*, Xiaolin Xu, Deliang Fan
  USENIX Security Symposium, 2021. (Acceptance rate 18.8%=248/1319)
  

• A Survey of Recent Attacks and Mitigation on FPGA Systems
  Shijin Duan, Wenhao Wang, Yukui Luo, Xiaolin Xu
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021 (Invited paper)
  

• DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA
  Yukui Luo*, Cheng Gongye*, Yunsi Fei, and Xiaolin Xu
  IEEE/ACM Design Automation Cnference (DAC) 2021. (Acceptance Rate: 23%)
  

• SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture (code)
  Ke Xia, Yukui Luo, Xiaolin Xu, and Sheng Wei
  IEEE/ACM Design Automation Cnference (DAC) 2021. (Acceptance Rate: 23%)
  

• CRAlert: Hardware-assisted Instruction-level Code Reuse Attack Detection
  Wenhao Wang, Xiaolin Xu, Jiliang Zhang
  IEEE Transactions on Circuits and Systems II, (TCAS-II) 2021

• FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA
  Yukui Luo, Shijin Duan, Xiaolin Xu
  ACM Transactions on Design Automation of Electronic Systems (TODAES), 2021.
  TODAES Rookie Author of the Year (RAY) Award

• Generating Random Keys for Cyber Physical System from Asynchronous Chaotic Topology
  Yukui Luo, Shijin Duan, Xiaolin Xu
  IEEE Cyber-Physical Systems Newsletter, 2021

• STT-MRAM-based Reliable Weak PUF
  Yupeng Hu, Linjun Wu, Zhuojun Chen, Yun Huang, Keqin Li, Xiaolin Xu, Jiliang Zhang
  IEEE Transactions on Computers (TC), 2021

• A Defense Framework Against Long-Wire-Based Secret Leakage in Cloud-FPGA
  Shijin Duan, Yukui Luo, Xiaolin Xu
  IEEE Cyber-Physical Systems Newsletter, 2021

• Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-Line
  Wenhao Wang, Yukui Luo, and Xiaolin Xu
  IEEE Design, Automation & Test in Europe (DATE), 2021.

2020

• Stealthy-Shutdown: Practical Remote Power Attacks in Multi-Tenant FPGAs
  Yukui Luo, Cheng Gongye, Shaolei Ren, Yunsi Fei, and Xiaolin Xu
  IEEE International Conference on Computer Design, (ICCD) 2020 (Acceptance Rate of full paper: 28%).

• A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA
  Yukui Luo, Xiaolin Xu
  IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020 (Acceptance Rate: 24%).

• A Privacy-Preserving-Oriented DNN Pruning and Mobile Acceleration Framework
  Yifan Gong, Zheng Zhan, Zhengang Li, Wei Niu, Xiaolong Ma, Wenhao Wang, Bin Ren, Caiwen Ding, Xue Lin, Xiaolin Xu, and Yanzhi Wang
  IEEE Great Lakes Symposium on VLSI (GLS-VLSI), 2020

• A Dynamic Frequency Scaling Framework AgainstReliability and Security Issues in Multi-tenant FPGA
  Yukui Luo, Xiaolin Xu
  International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2020 (poster presentation)

• Rethinking FPGA Security in the New Era of Artificial Intelligence
  Xiaolin Xu, Jiliang Zhang
  International Symposium on Quality Electronic Design (ISQED), 2020 (Invited paper)

• CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme (video)
  Bicky Shakya*, Xiaolin Xu*, Mark Tehranipoor, Domenic Forte
  International Conference on Cryptographic Hardware and Embedded Systems (CHES), 2020 (Acceptance Rate: 26.8%)

• A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology
  Yukui Luo*, Wenhao Wang*, Scott Best, Yanzhi Wang, Xiaolin Xu
  IEEE Transactions on Circuits and Systems I: Regular Papers, (TCAS-I) 2020.

2019

• HILL: A Hardware Isolation Framework against Information Leakage on Multi-Tenant FPGA Long-Wires
  Yukui Luo, Xiaolin Xu
  International Conference on Field-Programmable Technology (FPT), 2019

• An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology
  Scott Best, Xiaolin Xu
  IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2019 (Acceptance Rate: 23.9%).

• PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit based on Process Variations
  Shuo Li, Xiaolin Xu, Wayne Burleson
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019

• Chaos in a Ring Circuit
  Etienne Farcot, Scott Best, Roderick Edwards, Ismail Belgacem, Xiaolin Xu, Patrick Gill
  Chaos: An Interdisciplinary Journal of Nonlinear Science, 2019.

• Electronics Supply Chain Integrity Enabled by Blockchain
  Xiaolin Xu, Fahim Rahman, Bicky Shakya, Apostol Vassilev, Domenic Forte, Mark Tehranipoor
  ACM Transactions on Design Automation of Electronic Systems (TODAES), 2019.

2018 and earlier

• Power-based Side-Channel Instruction-level Disassembler
  Jungmin Park, Xiaolin Xu, Yier Jin, Domenic Forte, Mark Tehranipoor
  Design Automation Cnference (DAC), 2018 (Acceptance Rate: 24.3%)

• Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs
  Xiaolin Xu, Shahrzad Keshavarz, Domenic Forte, Mark Tehranipoor, Daniel Holcomb
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2018

• Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection
  Shahrzad Keshavarz, Cunxi Yu, Samaneh Ghandali, Xiaolin Xu, Daniel Holcomb
  Journal of Hardware and Systems Security (HaSS), 2018

• Development and Evaluation of Hardware Obfuscation Benchmarks
  Sarah Amir, Bicky Shakya, Xiaolin Xu, Yier Jin, Swarup Bhunia, Mark Tehranipoor, Domenic Forte
  Journal of Hardware and Systems Security (HaSS), 2018

• SCARe: An SRAM-based Countermeasure Against IC Recycling Framework
  Zimu Guo, Xiaolin Xu, Mark Tehranipoor, Domenic Forte
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018

• Aging Resistant RO PUF with Increased Reliability in FPGA
  Sreeja Chowdhury, Xiaolin Xu, Mark Tehranipoor, Domenic Forte
  International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2017

• MPA: Model-assisted PCB Attestation via Board-level RO and Temperature Compensation
  Zimu Guo, Xiaolin Xu, Mark Tehranipoor, Domenic Forte
  IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2017

• Novel Bypass Attack and BDD- based Tradeoff Analysis Against all Known Logic Locking Attacks
  Xiaolin Xu*, Bicky Shakya*, Mark Tehranipoor, Domenic Forte
  International Conference on Cryptographic Hardware and Embedded Systems (CHES), 2017 (Acceptance Rate: 25.3%).

• CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter
  Shuo Li, Xiaolin Xu, Wayne Burleson
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017

• FFD: A Framework for Fake Flash Detection
  Zimu Guo, Xiaolin Xu, Mark Tehranipoor, Domenic Forte
  Design Automation Conference (DAC), 2017 (Acceptance Rate: 22%)

• Security Beyond CMOS: Fundamentals, Applications, and Roadmap
  Fahim Rahman, Bicky Shakya, Xiaolin Xu, Domenic Forte, Mark Tehranipoor
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017

• Poly-Si Based Physical Unclonable Functions
  Haoting Shen, Fahim Rahman, Bicky Shakya, Xiaolin Xu, Mark Tehranipoor, Domenic Forte
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017

• Reliable PUF Design Using Failure Patterns from Time-Controlled Power Gating
  Xiaolin Xu, and Daniel Holcomb
  IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016

• Using Statistical Models to Improve the Reliability of Delay-Based PUFs
  Xiaolin Xu, Wayne Burleson, and Daniel E. Holcomb
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016

• A Clockless Sequential PUF with Autonomous Majority Voting
  Xiaolin Xu, and Daniel Holcomb
  IEEE Great Lakes Symposium on VLSI (GLS-VLSI), 2016

• Reliable Physical Unclonable Functions using Data Retention Voltage of SRAM Cells
  Xiaolin Xu, Amir Rahmati, Daniel Holcomb, Kevin Fu and Wayne Burleson
  Special section on hardware security and trust, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2015

• Security Evaluation and Enhancement of Bistable Ring PUFs
  Xiaolin Xu, Ulrich Rührmair, Daniel Holcomb, Wayne Burleson
  Proceedings of the 11th International Conference on Radio Frequency Identification: Security and Privacy issues (RFIDSec), 2015

• Virtual Proofs of Reality and their Physical Implementation
  Ulrich Ruhrmair, J L Martinez Hurtado, Xiaolin Xu, Christian Kraeh, Christian Hilgers, Dima Kononchuk, Jonathan J. Finley and Wayne Burleson
  IEEE Security and Privacy (Oakland), 2015 (Acceptance Rate: 13.5%)

• Efficient Power and Timing Side Channels for Physical Unclonable Functions
  Ulrich Ruhrmair*, Xiaolin Xu*, Jan Solter, Ahmed Mahmoud, Mehrdad Majzoobi, Farinaz Koushanfar and Wayne Burleson
  Cryptographic Hardware and Embedded Systems (CHES), 2014 (Acceptance Rate: 26%).

• Post-SiliconValidationand Calibration of Hardware Security Primitives
  XiaolinXu, Vikram Suresh, Raghavan Kumar, and Wayne Burleson
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014

• Hybrid Side-channel/machine-learning Attacks on PUFs: A new threat?
  Xiaolin Xu and Wayne Burleson
  Design, Automation & Test in Europe (DATE), 2014.

• PUF Modeling Attacks on Simulated and Silicon Data
  Ulrich Ruhrmair, Jan Solter, Frank Sehnke, Xiaolin Xu, Ahmed Mahmoud, Vera Stoyanova, Gideon Dror, Jurgen Schmidhuber, Wayne Burleson, Srinivas Devadas
  IEEE Transactions on Information Forensics and Security (TIFS), 2013

• Robust and Low-Power Delay-Based Physical Unclonable Function Design
  Xiaolin Xu, Raghavan Kumar and Wayne Burleson
  Semiconductor Research Corporation (SRC) TECHCON Conference, 2012

Book Chapter

• Machine Learning in Hardware Security
  Shijin Duan, Zhengang Li, Yukui Luo, Mengshu Sun, Wenhao Wang, Xue Shelley Lin, Xiaolin Xu
  In book “Emerging Topics in Hardware Security”, Springer, 2021.

• When the Physical Disorder of CMOS Meets Machine Learning
  Xiaolin Xu, Shuo Li, Raghaven Kumar, Wayne Burleson
  In book “High-Speed and Low Power Technologies: Electronics & Photonics”, CRC Press, 2018.

• Leveraging Circuit Edit for Low Volume Trusted Fabrication
  Bicky Shakya, Xiaolin Xu, Navid Asadizanjani, Mark Tehranipoor, Domenic Forte
  In book “Security Opportunities by Nano Devices and Emerging Technologies”, CRC Press, 2017

• Physically unclonable functions: A Window into CMOS Process Variations
  Raghavan Kumar, Xiaolin Xu, Wayne Burleson
  In book “Circuits and Systems for Security and Privacy ”, CRC Press, 2016.

Dissertation

• Intrinsic Functions for Securing CMOS Computation: Variability, Modeling and Noise Sensitivity, UMass Amherst, 2016.